With the evolution of photoelectricity and semiconductor techniques, vigorous development is also brought to a display panel field. In the existing display field, commonly seen displays are a liquid crystal display, an organic light emitting diode display, and the like. In current active display panels, a driving signal from a driving circuit outside a display panel is utilized to drive a chip on the display panel so as to display an image. Recently, in order to narrow a frame of a display panel, it gradually develops into directly manufacturing a driving circuit on the display panel, such as, integrating a gate driving circuit on a substrate to form scanning of the display panel by using a Gate Drive on Array (GOA for short).
Compared with a conventional COF (Chip On Film) technique, a GOA technique may not only reduce manufacturing costs significantly but also be highly advantageous to improving product capacity for omitting manufacturing procedure of bonding of the COF at a Gate side, moreover, it may make the display panel be more suitable for manufacturing a narrow-frame or frameless display products. Therefore, the GOA technique is a key technique in future development of display panels.
FIG. 1 illustrates a schematic circuit diagram of a single-level GOA circuit in the prior art. A GOA circuit usually includes a plurality of single-level GOA circuits that are cascaded, and the GOA circuit of each level drives a horizontal scanning line of a level correspondingly. As illustrated in FIG. 1, a single-level GOA circuit 100 includes a pull-up control unit 110, a pull-up unit 120, a signal downward transmission unit 130, a pull-down unit 140, a pull-down maintaining unit 150 and a bootstrap unit 160, wherein the pull-up control unit 110 takes charge of pre-charging a first node Q(N), the pull-up unit 120 is mainly for increasing a potential of a scan signal output end G(N) so as to control the turning on of a transistor of the pull-down unit of an upper-level GOA circuit, the signal downward transmission unit 130 is mainly for controlling transmission and cutoff of a scan signal in the pull-up control unit 110 of a lower-level GOA circuit, the pull-down unit 140 takes charge of pulling down a potential of the first node Q(N) and a potential of the scan signal output end G(N) to a potential of a first voltage input end VSS at a first time, the pull-down maintaining unit 150 takes charge of maintaining the potential of the first node Q(N) and the potential of the scan signal output end G(N) to be the potential of the first voltage input end VSS unchanged, and the bootstrap unit 160 takes charge of increasing the potential of the first node Q(N); in this way, it is conducive to an output of the potential of the scan signal output end G(N) of the pull-up unit 120. The potential of the first voltage input end VSS may be a low potential, for example, may be a ground voltage.
An electronic element in the pull-down maintaining unit 150 illustrated in FIG. 1 is actually an inverter of a Darlington structure, and a specific circuit thereof is as illustrated in FIG. 2. FIG. 2 illustrates a schematic circuit diagram of an inverter of a Darlington structure in the prior art. In the circuit diagram of the inverter of a Darlington structure, when a low level signal is input at the first voltage input end VSS, a high level signal is input at a pull-down signal input end LC. When a high level signal is input at an inverter input end Input, a low level signal is output at an inverter output end Output. In contrary, when a low level signal is input at the inverter input end Input, a high level signal is output at the inverter output end Output.
In the prior art, a single-level GOA circuit is basically to place the above several parts in a GOA circuit of a same level, thus, the single-level GOA circuit in FIG. 1 may be converted into a single-level GOA circuit illustrated in FIG. 3. FIG. 3 illustrates another schematic circuit diagram of a single-level GOA circuit in the prior art. In FIG. 3, CK/XCK denotes a clock signal input end, ST(N) denotes a level transmission signal output end, G(N) denotes a scan signal output end, and Q(N) denotes a first node. A high level signal may be input at the pull-down signal input end LC, a low level signal may be input at the first voltage input end VSS, and a potential of the first node Q(N) may be an alternating current potential.
When the potential of the first node Q(N) is a low potential, a second transistor T52 and a fourth transistor T54 are turned off, a first transistor T51 is turned on, and then a third transistor T53 is turned on, and a potential of point B is a high potential. When the potential of the first node Q(N) is a high potential, the second transistor T52 is turned on, and the first transistor T51 is turned on, at this time, a potential of point A is in a certain intermediate potential for being subject to mutual pulling between a high potential of the pull-down signal input end LC and a low potential of the first voltage input end VSS, the third transistor T53 is in a semi-turned-on state, and the fourth transistor T54 is in a turned-on state. Therefore, a potential of point B is not possible to satisfy requirements of an absolute low potential for also being subject to mutual pulling between a potential of the pull-down signal input end LC and a potential of the first voltage input end VSS.